ABR has designed an innovative chip, the ABR TSP (Time Series Processor - https://appliedbrainresearch.com/products/tsp/ ), for speech recognition, natural language processing, and any other time series data. The TSP has the goal of delivering cloud-quality time-series inference for use in sensor data processing and dialog systems implementations at the edge. For speech processing, ABR's TSP will run BERT-sized NLP models at less than 60 mW SoC level power. Device makers can deliver low-power, low-latency, low-cost, real-time voice interfaces that save costs over CPUs and GPUs. For the same price as a keyword spotter chip, the TSP can move speech interactions to natural conversation from keyword-spotting, increasing customer satisfaction. For IoT uses, the TSP delivers larger models comparable with CPUs and GPUs, for less cost and with more accuracy and lower latency than using an MPU. ABR's TSP implements ABR's patented Legendre Memory Unit (LMU) algorithm which enables smaller ASR and NLP models. We will discuss ABR's LMU algorithm and the uses of the TSP chip for edge NLP and ASR, with examples.

The edge and embedded AI market is diverse and distributed, where systems that adopted industry standards have accelerated growth and lowered the barrier to entry.

With the emergence of AI accelerators and systems, it is important to learn from what has worked in the embedded space and leverage standards that enable developers and applications, reduce risk, and accelerate time to market. In this talk, we will outline some of the challenges to AI system adoption and how Flex Logix is working to make AI customization and deployment easier.

Edge AI is going to play a significant role in many areas such as automotive, smart home, smart cities, education, robotics, and surveillance, to name a few. The past few years have seen a rise in the number of HW options designed for accelerating AI inference at the edge. These multiple HW options, however, have made application development for the edge complicated. Each HW option comes with its own inference runtime, model porting SW, operator support, optimizations, and model zoo making it  a time consuming effort to evaluate the HW. Performance metrics are not standardized across HW options and even for a fixed HW, they vary depending on the model and the host system. All these factors make evaluating edge HW a challenging task. In this talk, we will provide an overview of these challenges as well as our attempts to alleviate these problems.

Designing hardware architectures for artificial intelligence acceleration (AI) at the edge is hard, especially for achieving the combination of high energy-efficiency and performance.  The reason Edge AI is so difficult today, is that it’s really a systems challenge, with a heterogenous mixture of software, hardware processors and diverse applications.  Codesigning a robust sy stem software stack that works across such heterogeneity, together with an efficient and scalable processor architecture is often neglected and poses a bigger challenge. 

In this talk we will describe howEdgeCortix is bridging this software & hardware divide, going beyond theoretical performance metrics, with the combination of a robust compiler, scheduler, runtime engine, and a reconfigurable co-processor. Using edge AI use-case examples, this presentation will describe how the combination of our MERA™ software (framework) and first-generation SAKURA-AI™ co-processor  achieves high efficiency, while also effectively hiding the hardware complexity, delivering a compelling solution tailored for the needs of todays edge AI application developers.