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The true potential of AI rests on super-human learning capacity, and on the ability to selectively draw on that learning. Both of these properties – scale and selectivity – challenge the design of AI computers and the tools used to program them. A rich pool of new ideas is emerging, driven by a new breed of computing company, according to Graphcore co-founder Simon Knowles. At the AI Hardware Summit, Phil Brown, VP Scaled Systems Product discusses the creation of the Intelligence Processing Unit (IPU) – a new type of processor, specifically designed for AI computation. He looks ahead, towards the development of AIs with super-human cognition, and explores the nature of computation systems needed to make powerful AI an economic everyday reality.

Developer Efficiency
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Phil Brown

VP, Scaled Systems Product
Graphcore

Phil leads Graphcore’s efforts to build large scale AI/ML processing capability using Graphcore unique Intelligence Processing Units (IPUs) and IPU-Fabric and Streaming Memory technology. Previously he has held a number of different roles at Graphcore including Director of Applications, leading development of Graphcore’s flagship AL/ML models, and Director of Field Engineering, which acts as the focal point for technical engagements with our customers. Prior to joining Graphcore, Phil worked for Cray Inc. in a number of roles, including leading their engagement with the weather forecasting and climate research customers worldwide and as a technical architect. Phil holds a PhD in Computational Chemistry from the University of Bristol.

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Phil Brown

VP, Scaled Systems Product
Graphcore

Phil leads Graphcore’s efforts to build large scale AI/ML processing capability using Graphcore unique Intelligence Processing Units (IPUs) and IPU-Fabric and Streaming Memory technology. Previously he has held a number of different roles at Graphcore including Director of Applications, leading development of Graphcore’s flagship AL/ML models, and Director of Field Engineering, which acts as the focal point for technical engagements with our customers. Prior to joining Graphcore, Phil worked for Cray Inc. in a number of roles, including leading their engagement with the weather forecasting and climate research customers worldwide and as a technical architect. Phil holds a PhD in Computational Chemistry from the University of Bristol.

Developer Efficiency
Enterprise AI
ML at Scale
NLP
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Kunle Olukotun

Chief Technologist & Co-Founder
SambaNova Systems

Kunle Olukotun is the Cadence Design Professor of Electrical Engineering and Computer Science at Stanford University. Olukotun is a renowned pioneer in multi-core processor design and the leader of the Stanford Hydra chip multiprocessor (CMP) research project.

Prior to SambaNova Systems, Olukotun founded Afara Websystems to develop high-throughput, low-power multi-core processors for server systems. The Afara multi-core processor, called Niagara, was acquired by Sun Microsystems and now powers Oracle’s SPARC-based servers.

Olukotun is the Director of the Pervasive Parallel Lab and a member of the Data Analytics for What’s Next (DAWN) Lab, developing infrastructure for usable machine learning.

Olukotun is an ACM Fellow and IEEE Fellow for contributions to multiprocessors on a chip and multi-threaded processor design. Olukotun recently won the prestigious IEEE Computer Society’s Harry H. Goode Memorial Award and was also elected to the National Academy of Engineering—one of the highest professional distinctions accorded to an engineer.

Kunle received his Ph.D. in Computer Engineering from The University of Michigan.

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Kunle Olukotun

Chief Technologist & Co-Founder
SambaNova Systems

Kunle Olukotun is the Cadence Design Professor of Electrical Engineering and Computer Science at Stanford University. Olukotun is a renowned pioneer in multi-core processor design and the leader of the Stanford Hydra chip multiprocessor (CMP) research project.

Prior to SambaNova Systems, Olukotun founded Afara Websystems to develop high-throughput, low-power multi-core processors for server systems. The Afara multi-core processor, called Niagara, was acquired by Sun Microsystems and now powers Oracle’s SPARC-based servers.

Olukotun is the Director of the Pervasive Parallel Lab and a member of the Data Analytics for What’s Next (DAWN) Lab, developing infrastructure for usable machine learning.

Olukotun is an ACM Fellow and IEEE Fellow for contributions to multiprocessors on a chip and multi-threaded processor design. Olukotun recently won the prestigious IEEE Computer Society’s Harry H. Goode Memorial Award and was also elected to the National Academy of Engineering—one of the highest professional distinctions accorded to an engineer.

Kunle received his Ph.D. in Computer Engineering from The University of Michigan.

Author:

Rodrigo Liang

Co-Founder & CEO
SambaNova Systems

Rodrigo is CEO and co-founder of SambaNova Systems. Prior to joining SambaNova, Rodrigo was responsible for SPARC Processor and ASIC Development at Oracle. He led the engineering organization responsible for the design of state-of-the-art processors and ASIC's for Oracle's enterprise servers.

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Rodrigo Liang

Co-Founder & CEO
SambaNova Systems

Rodrigo is CEO and co-founder of SambaNova Systems. Prior to joining SambaNova, Rodrigo was responsible for SPARC Processor and ASIC Development at Oracle. He led the engineering organization responsible for the design of state-of-the-art processors and ASIC's for Oracle's enterprise servers.

Cerebras Systems builds the fastest AI accelerators in the industry. In this talk we will review how the size and scope of massive natural language processing (NLP) presents fundamental challenges to legacy compute and to traditional cloud providers. We will explore the importance of guaranteed node to node latency in large clusters, how that can’t be achieved in the cloud, and how it prevents linear and even deterministic scaling. We will examine the complexity of distributing NLP models over hundreds or thousands of GPUs and show how quickly and easily a cluster of Cerebras CS-2s is set up, and how linear scaling can be achieved over millions of compute cores with Cerebras technology. And finally, we will show how innovative customers are using clusters of Cerebras CS-2s to train large language models in order to solve both basic and applied scientific challenges, including understanding the COVID-19 replication mechanism, epigenetic language modelling for drug discovery, and in the development of clean energy. This enables researchers to test ideas that may otherwise languish for lack of resources and, ultimately, reduces the cost of curiosity.  ​

 

Chip Design
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Andy Hock

VP, Product Management
Cerebras

Dr. Andy Hock is VP of Product Management at Cerebras Systems with responsibility for product strategy. His organization drives engagement with engineering and our customers to inform the hardware, software, and machine learning technical requirements and accelerate world-leading AI with Cerebras’ products. Prior to Cerebras, Andy has held senior leadership positions with Arete Associates, Skybox Imaging (acquired by Google), and Google. He holds a PhD in Geophysics and Space Physics from UCLA.

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Andy Hock

VP, Product Management
Cerebras

Dr. Andy Hock is VP of Product Management at Cerebras Systems with responsibility for product strategy. His organization drives engagement with engineering and our customers to inform the hardware, software, and machine learning technical requirements and accelerate world-leading AI with Cerebras’ products. Prior to Cerebras, Andy has held senior leadership positions with Arete Associates, Skybox Imaging (acquired by Google), and Google. He holds a PhD in Geophysics and Space Physics from UCLA.

Chip Design
Edge AI
Enterprise AI
ML at Scale
NLP
Novel AI Hardware
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering
Industry & Investment

Author:

Lip-Bu Tan

Founder & Chairman
Walden International

Lip-Bu Tan is Founder and Chairman of Walden International (“WI”), and Founding Managing Partner of Celesta Capital and Walden Catalyst Ventures, with over $5 billion under management.  He formerly served as Chief Executive Officer and Executive Chairman of Cadence Design Systems, Inc.  He currently serves on the Board of Schneider Electric SE (SU: FP), Intel Corporation (NASDAQ: INTC), and Credo Semiconductor (NASDAQ: CRDO).

 

Lip-Bu focuses on semiconductor/components, cloud/edge infrastructure, data management and security, and AI/machine learning.Lip-Bu received his B.S. from Nanyang University in Singapore, his M.S. in Nuclear Engineering from the Massachusetts Institute of Technology, and his MBA from the University of San Francisco. He also received his honorary degree for Doctor of Humane Letters from the University of San Francisco.  Lip-Bu currently serves on Carnegie Mellon University (CMU)’s Board of Trustees and the School of Engineering Dean’s Council, Massachusetts Institute of Technology (MIT)’s School of Engineering Dean’s Advisory Council, University of California Berkeley (UCB)’s College of Engineering Advisory Board and their Computing, Data Science, and Society Advisory Board, and University of California San Francisco (UCSF)’s Executive Council. He’s also a member of the Global Advisory Board of METI Japan, The Business Council, and Committee 100. He also served on the board of the Board of Global Semiconductor Alliance (GSA) from 2009 to 2021, and as a Trustee of Nanyang Technological University (NTU) in Singapore from 2006 to 2011.  Lip-Bu has been named one of the Top 10 Venture Capitalists in China by Zero2ipo and was listed as one of the Top 50 Venture Capitalists on the Forbes Midas List. He’s the recipient of imec’s 2023 Lifetime of Innovation Award, the Semiconductor Industry Association (SIA) 2022 Robert N. Noyce Award, and GSA’s 2016 Dr. Morris Chang's Exemplary Leadership Award.  In 2017, he was ranked #1 of the most well-connected executives in the technology industry by the analytics firm Relationship Science. 

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Lip-Bu Tan

Founder & Chairman
Walden International

Lip-Bu Tan is Founder and Chairman of Walden International (“WI”), and Founding Managing Partner of Celesta Capital and Walden Catalyst Ventures, with over $5 billion under management.  He formerly served as Chief Executive Officer and Executive Chairman of Cadence Design Systems, Inc.  He currently serves on the Board of Schneider Electric SE (SU: FP), Intel Corporation (NASDAQ: INTC), and Credo Semiconductor (NASDAQ: CRDO).

 

Lip-Bu focuses on semiconductor/components, cloud/edge infrastructure, data management and security, and AI/machine learning.Lip-Bu received his B.S. from Nanyang University in Singapore, his M.S. in Nuclear Engineering from the Massachusetts Institute of Technology, and his MBA from the University of San Francisco. He also received his honorary degree for Doctor of Humane Letters from the University of San Francisco.  Lip-Bu currently serves on Carnegie Mellon University (CMU)’s Board of Trustees and the School of Engineering Dean’s Council, Massachusetts Institute of Technology (MIT)’s School of Engineering Dean’s Advisory Council, University of California Berkeley (UCB)’s College of Engineering Advisory Board and their Computing, Data Science, and Society Advisory Board, and University of California San Francisco (UCSF)’s Executive Council. He’s also a member of the Global Advisory Board of METI Japan, The Business Council, and Committee 100. He also served on the board of the Board of Global Semiconductor Alliance (GSA) from 2009 to 2021, and as a Trustee of Nanyang Technological University (NTU) in Singapore from 2006 to 2011.  Lip-Bu has been named one of the Top 10 Venture Capitalists in China by Zero2ipo and was listed as one of the Top 50 Venture Capitalists on the Forbes Midas List. He’s the recipient of imec’s 2023 Lifetime of Innovation Award, the Semiconductor Industry Association (SIA) 2022 Robert N. Noyce Award, and GSA’s 2016 Dr. Morris Chang's Exemplary Leadership Award.  In 2017, he was ranked #1 of the most well-connected executives in the technology industry by the analytics firm Relationship Science. 

Developer Efficiency
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Alexis Black Bjorlin

VP/GM, DGX Cloud
NVIDIA

Dr. Alexis Black Bjorlin was previously VP, Infrastructure Hardware Engineering at Meta. She also serves on the board of directors at Digital Realty and Celestial AI. Prior to Meta, Dr. Bjorlin was Senior Vice President and General Manager of Broadcom’s Optical Systems Division and previously Corporate Vice President of the Data Center Group and General Manager of the Connectivity Group at Intel. Prior to Intel, she spent eight years as President of Source Photonics, where she also served on the board of directors. She earned a B.S. in Materials Science and Engineering from Massachusetts Institute of Technology and a Ph.D. in Materials Science from the University of California at Santa Barbara.

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Alexis Black Bjorlin

VP/GM, DGX Cloud
NVIDIA

Dr. Alexis Black Bjorlin was previously VP, Infrastructure Hardware Engineering at Meta. She also serves on the board of directors at Digital Realty and Celestial AI. Prior to Meta, Dr. Bjorlin was Senior Vice President and General Manager of Broadcom’s Optical Systems Division and previously Corporate Vice President of the Data Center Group and General Manager of the Connectivity Group at Intel. Prior to Intel, she spent eight years as President of Source Photonics, where she also served on the board of directors. She earned a B.S. in Materials Science and Engineering from Massachusetts Institute of Technology and a Ph.D. in Materials Science from the University of California at Santa Barbara.

Author:

Marshall Choy

SVP, Product
SambaNova Systems

Marshall Choy is Senior Vice President of Product at SambaNova Systems and is responsible for product management and go-to-market operations.  Marshall has extensive experience leading global organizations to bring breakthrough products to market, establish new market presences, and grow new and existing lines of business.  Marshall was previously Vice President of Product Management at Oracle until 2018.  He was responsible for the portfolio and strategy for Oracle Systems products and solutions.  He led teams that delivered comprehensive end-to-end hardware and software solutions and product management operations.  Prior to joining Oracle in 2010 when it acquired Sun Microsystems, he served as Director of Engineered Solutions at Sun.  During his 11 years there, Marshall held various positions in development, information technology, and marketing. 

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Marshall Choy

SVP, Product
SambaNova Systems

Marshall Choy is Senior Vice President of Product at SambaNova Systems and is responsible for product management and go-to-market operations.  Marshall has extensive experience leading global organizations to bring breakthrough products to market, establish new market presences, and grow new and existing lines of business.  Marshall was previously Vice President of Product Management at Oracle until 2018.  He was responsible for the portfolio and strategy for Oracle Systems products and solutions.  He led teams that delivered comprehensive end-to-end hardware and software solutions and product management operations.  Prior to joining Oracle in 2010 when it acquired Sun Microsystems, he served as Director of Engineered Solutions at Sun.  During his 11 years there, Marshall held various positions in development, information technology, and marketing. 

AI Hardware Summit attendees are invited to attend the an extended networking session where they can meet attendees from across both events. The Meet & Greet is a perfect opportunity to reconnect with peers, expand your network, and discuss the state of ML across the cloud-edge continuum!

Chip Design
Developer Efficiency
Edge AI
Enterprise AI
ML at Scale
NLP
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Colin Murdoch

Chief Business Officer
DeepMind

Decades of international commercial experience and deep technical expertise mean Colin is uniquely placed to ensure DeepMind’s cutting-edge research benefits as many people as possible. As Chief Business Officer of DeepMind, he oversees a wide-range of teams including Applied, which applies research breakthroughs to Google products and infrastructure used by billions of people. He also helps drive the growth of DeepMind, building and leading critical functions including finance and strategy and leading external and commercial partnerships. Originally an electronics and software engineer, he has held senior positions at both start-ups and global companies such as Thomson Reuters, helping them solve their own complex, mission-critical, real-world challenges.

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Colin Murdoch

Chief Business Officer
DeepMind

Decades of international commercial experience and deep technical expertise mean Colin is uniquely placed to ensure DeepMind’s cutting-edge research benefits as many people as possible. As Chief Business Officer of DeepMind, he oversees a wide-range of teams including Applied, which applies research breakthroughs to Google products and infrastructure used by billions of people. He also helps drive the growth of DeepMind, building and leading critical functions including finance and strategy and leading external and commercial partnerships. Originally an electronics and software engineer, he has held senior positions at both start-ups and global companies such as Thomson Reuters, helping them solve their own complex, mission-critical, real-world challenges.

Author:

Cade Metz

Technology Correspondent
New York Times

Cade Metz is a reporter with The New York Times, covering artificial intelligence, driverless cars, robotics, virtual reality, and other emerging areas. Genius Makers is his first book. Previously, he was a senior staff writer with Wired magazine and the U.S. editor of The Register, one of Britain’s leading science and technology news sites.

A native of North Carolina and a graduate of Duke University, Metz, 48, works in The New York Times’ San Francisco bureau and lives across the bay with his wife Taylor and two daughters.

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Cade Metz

Technology Correspondent
New York Times

Cade Metz is a reporter with The New York Times, covering artificial intelligence, driverless cars, robotics, virtual reality, and other emerging areas. Genius Makers is his first book. Previously, he was a senior staff writer with Wired magazine and the U.S. editor of The Register, one of Britain’s leading science and technology news sites.

A native of North Carolina and a graduate of Duke University, Metz, 48, works in The New York Times’ San Francisco bureau and lives across the bay with his wife Taylor and two daughters.

2022 Sample Attendee List

Graphcore's Intelligence Processing Unit (IPU), built on its unique wafer-on-wafer technology architecture, enables innovators across all industries to undertake breakthrough research with the power of AI compute. To deliver what Graphcore believes will be the standard for machine intelligence compute, it follows a continuous integration (CI) and continuous delivery (CD) process to ensure incremental code changes are delivered quickly and reliably to production. In this workshop, Graphcore will share how it’s using Synopsys formal verification solutions throughout the CI/CD process to deliver bug-free silicon.  Workshop topics include:

  • An introduction to Sequential Equivalence Checking (SEQ) and Formal Testbench Analyzer (FTA) applications, part of Synopsys VC Formal
  • Graphcore’s formal verification deployment to maximize engineering productivity
  • How formal is modified for CI and CD
  • Strategies Graphcore employed to overcome reproducibility challenges at the CI stage

 

Hardware Engineer workshop are restricted to hardware engineers and architects, and software designers from companies interested in learning how to design and deploy ML onto hardware platforms.

Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a hardware or software engineer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.

Chip Design
Novel AI Hardware
Systems Design
Hardware Engineering
Systems Engineering

Author:

Manish Pandey

Fellow & VP, R&D
Synopsys

Manish Pandey is Vice President R&D and Fellow at Synopsys, and an Adjunct Professor at Carnegie Mellon University. He completed his PhD in Computer Science from Carnegie Mellon University and a B. Tech. in Computer Science from the Indian Institute of Technology Kharagpur. He currently leads the R&D teams for formal and static technologies, and machine learning at Synopsys. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry. Manish has been the recipient of the IEEE Transaction in CAD Outstanding Young author award and holds over two dozen patents and refereed publications.

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Manish Pandey

Fellow & VP, R&D
Synopsys

Manish Pandey is Vice President R&D and Fellow at Synopsys, and an Adjunct Professor at Carnegie Mellon University. He completed his PhD in Computer Science from Carnegie Mellon University and a B. Tech. in Computer Science from the Indian Institute of Technology Kharagpur. He currently leads the R&D teams for formal and static technologies, and machine learning at Synopsys. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry. Manish has been the recipient of the IEEE Transaction in CAD Outstanding Young author award and holds over two dozen patents and refereed publications.

Author:

Anthony Wood

Formal Verification Lead
Graphcore

Anthony has held a number of a design and verification roles working on CPUs, GPUs and IPUs at Infineon, Xmos, Imagination and Graphcore.  At Imagination he was head of verification for the high-end GPU cores.  At Graphcore his responsibilities include leveraging formal verification techniques throughout the silicon team; reducing delivery timescales through Continuous Delivery; and working to ensure verification disciplines are adopted for DFT.  He strives to find ways of improving the productivity of silicon engineers and of course he agonises about potential verification holes.

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Anthony Wood

Formal Verification Lead
Graphcore

Anthony has held a number of a design and verification roles working on CPUs, GPUs and IPUs at Infineon, Xmos, Imagination and Graphcore.  At Imagination he was head of verification for the high-end GPU cores.  At Graphcore his responsibilities include leveraging formal verification techniques throughout the silicon team; reducing delivery timescales through Continuous Delivery; and working to ensure verification disciplines are adopted for DFT.  He strives to find ways of improving the productivity of silicon engineers and of course he agonises about potential verification holes.